Engineer

RESPONSIBILITIES: • Lead and define overall test chip architecture, including the functional and DFX aspects. • Integrate high speed DDR PHY IPs into test chip top level RTL which requires working knowledge of DDR/LPDDR/HBM etc. protocols. • Develop additional custom logic at test chip top level for interfacing and interacting with PHY IPs and associated logic. • Implementation of SOC DFT features (TAP controller, JTAG/IJTAG, GPIOs, ESD structures etc) into RTL. • Gate level simulation using Synopsys VCS and Verdi. • SOC-level SDC development and hand-off to PD • UPF development and hand-off to PD. • ATPG patterns translation from IP level to SOC level and hand-off. • Spyglass bring up and analysis for scan readiness/test coverage gaps. • Run all SOC RTL QA checks (Lint/CDC/RDC/VCLP etc.) • Support silicon bringup and debug. • Develop efficient DFx flows and methodology compatible with front end and physical design flows Essential Skills: THE ROLE: Circuit Technology team is looking for a passionate and experienced test chip RTL execution Lead for our high speed PHYs as well as other IPs. This opportunity includes ownership of defining the overall test chip architecture, RTL coding, supporting scan stitching, timing constraints development, supporting ATPG as well as post-silicon bringup.KEY RESPONSIBILITIES: • Lead and define overall test chip architecture, including the functional and DFX aspects. • Integrate high speed DDR PHY IPs into test chip top level RTL which requires working knowledge of DDR/LPDDR/HBM etc. protocols. • Develop additional custom logic at test chip top level for interfacing and interacting with PHY IPs and associated logic. • Implementation of SOC DFT features (TAP controller, JTAG/IJTAG, GPIOs, ESD structures etc) into RTL. • Gate level simulation using Synopsys VCS and Verdi. • SOC-level SDC development and hand-off to PD • UPF development and hand-off to PD. • ATPG patterns translation from IP level to SOC level and hand-off. • Spyglass bring up and analysis for scan readiness/test coverage gaps. • Run all SOC RTL QA checks (Lint/CDC/RDC/VCLP etc.) • Support silicon bringup and debug. • Develop efficient DFx flows and methodology compatible with front end and physical design flows